Synopsys Off Campus Drive 2026: Join Synopsys Off Campus Drive 2026 for Internship roles! Freshers eligible – check eligibility, salary, last date & apply online now. Top VLSI/EDA jobs for 2026 batch in Hyderabad/Bangalore. Don’t miss Synopsys freshers hiring!
About Company: Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.
Job Title: Internship
Location: Bangalore
| Freshers Jobs by City |
|---|
| Bangalore Jobs |
| Chennai Jobs |
| Delhi NCR Jobs |
| Hyderabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
Job Description:
- Designing DDR I/O circuits and layouts for advanced semiconductor applications.
- Collaborating with internal development teams to ensure high-quality product outcomes.
- Applying knowledge of CMOS circuit design, layout methodology, and flow to assigned projects.
- Supporting the execution of circuit design tasks with a focus on efficiency and quality.
- Contributing to the understanding and implementation of JEDEC requirements for DDR interfaces and standards.
Requirements:
- Recently completed a BE/BTech in Electrical & Electronics Engineering (EEE) or Electronics & Communication Engineering (ECE) from class of 2025.
- Knowledge of CMOS processes and deep submicron process technology challenges.
- Understanding of CMOS circuit design, layout methodology, and analog/mixed signal circuitry.
- Familiarity with basic ESD concepts is an advantage.
- Experience or coursework related to ASIC design flow.
- Knowledge of JEDEC requirements for DDR interfaces, DDR Timing, ODT, and SDRAM functionality is a plus.
- Ability to efficiently execute assigned circuit design tasks with attention to product quality.
- Strong written and verbal communication skills for effective teamwork.
Join Our Telegram Group for Instant Job Notification
Qualification: B.E / B.Tech (2025 batch)
Work Experience: Freshers
How to Apply for Synopsys Off Campus Drive 2026?
Interested and Eligible candidates can apply for this drive online by using the link below.
Apply: Click Here